1. Field of the Invention
The present invention relates to programmable logic arrays and more particularly to such arrays having a feedback circuit for connecting an output of the array to an input of the array, to provide sequential logic.
2. The Prior Art
Programmable logic arrays have been described in "MOS/LSI Design and Application," by W. Carr & J. Mize, published by McGraw-Hill Book Co., New York, 1972. On pages 229-258 a logic arrangement is described consisting of an AND-gate matrix, an OR-gate matrix, and associated feedback and output circuits. The provision of a feedback loop makes it possible for the output of the logic array to depend not only on the instantaneous inputs, but also on the inputs to the logic array during a previous time interval. The AND-gate matrix and the OR-gate matrix consist of fixed word storage devices, with load transistors connected as resistances, by which the capacitances at the outputs of the gates of the fixed word storage devices are charged. This arrangement places a relatively low limit on the operating speed of the array, and also limits the packing density which can be obtained.
It is, therefore, desirable to provide a programmable logic array which is capable of faster operation, and in which a greater packing density can be achieved.